Commit 11f81055 authored by Naga Sureshkumar Relli's avatar Naga Sureshkumar Relli
Browse files

kernel: update node alignments



some of the device nodes in zynqmp.dtsi and zynq-7000.dtsi are not properly
aligned. i.e no tabs and change in order of node properties. so that everyting
will be in sync with kernel dtsi files
Signed-off-by: default avatarNaga Sureshkumar Relli <nagasure@xilinx.com>
Acked-by: default avatarMichal Simek <michals@xilinx.com>
parent 6c124f12
...@@ -99,10 +99,10 @@ ...@@ -99,10 +99,10 @@
gpio0: gpio@e000a000 { gpio0: gpio@e000a000 {
compatible = "xlnx,zynq-gpio-1.0"; compatible = "xlnx,zynq-gpio-1.0";
#gpio-cells = <2>; #gpio-cells = <2>;
#interrupt-cells = <2>;
clocks = <&clkc 42>; clocks = <&clkc 42>;
gpio-controller; gpio-controller;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
interrupts = <0 20 4>; interrupts = <0 20 4>;
reg = <0xe000a000 0x1000>; reg = <0xe000a000 0x1000>;
...@@ -330,10 +330,10 @@ ...@@ -330,10 +330,10 @@
interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
"dma4", "dma5", "dma6", "dma7"; "dma4", "dma5", "dma6", "dma7";
interrupts = <0 13 4>, interrupts = <0 13 4>,
<0 14 4>, <0 15 4>, <0 14 4>, <0 15 4>,
<0 16 4>, <0 17 4>, <0 16 4>, <0 17 4>,
<0 40 4>, <0 41 4>, <0 40 4>, <0 41 4>,
<0 42 4>, <0 43 4>; <0 42 4>, <0 43 4>;
#dma-cells = <1>; #dma-cells = <1>;
#dma-channels = <8>; #dma-channels = <8>;
#dma-requests = <4>; #dma-requests = <4>;
...@@ -342,12 +342,12 @@ ...@@ -342,12 +342,12 @@
}; };
devcfg: devcfg@f8007000 { devcfg: devcfg@f8007000 {
clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
compatible = "xlnx,zynq-devcfg-1.0"; compatible = "xlnx,zynq-devcfg-1.0";
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
interrupts = <0 8 4>; interrupts = <0 8 4>;
reg = <0xf8007000 0x100>; reg = <0xf8007000 0x100>;
clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
syscon = <&slcr>; syscon = <&slcr>;
}; };
......
...@@ -209,10 +209,12 @@ ...@@ -209,10 +209,12 @@
#power-domain-cells = <0x0>; #power-domain-cells = <0x0>;
pd-id = <0x30>; pd-id = <0x30>;
}; };
pd_pcie: pd-pcie { pd_pcie: pd-pcie {
#power-domain-cells = <0x0>; #power-domain-cells = <0x0>;
pd-id = <0x3b>; pd-id = <0x3b>;
}; };
pd_gpu: pd-gpu { pd_gpu: pd-gpu {
#power-domain-cells = <0x0>; #power-domain-cells = <0x0>;
pd-id = <0x3a 0x14 0x15>; pd-id = <0x3a 0x14 0x15>;
...@@ -438,7 +440,10 @@ ...@@ -438,7 +440,10 @@
power-domains = <&pd_gpu>; power-domains = <&pd_gpu>;
}; };
/* ADMA */ /* LPDDMA default allows only secured access. inorder to enable
* These dma channels, Users should ensure that these dma
* Channels are allowed for non secure access.
*/
lpd_dma_chan1: dma@ffa80000 { lpd_dma_chan1: dma@ffa80000 {
status = "disabled"; status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0"; compatible = "xlnx,zynqmp-dma-1.0";
......
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